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Tuesday, Oct 7th
1:00pm - 4:05pm MT
The Convergence of Semiconductor Manufacturing and Design
Location: West Building, 100 Level, Room 101 C
Design
Tuesday, Oct 7th
1:00pm - 1:05pm MT
Welcome Remarks
Location: West Building, 100 Level, Room 101 C
Session Moderator (Design): Bob Smith – SEMI
Design
Tuesday, Oct 7th
1:05pm - 1:10pm MT
Session Overview
Location: West Building, 100 Level, Room 101 C
Session Moderator (Design): Ming Zhang – PDF Solutions
Design
Tuesday, Oct 7th
1:10pm - 1:30pm MT
Revolutionizing Silicon to Systems Design: Unlocking the Future with 2.5D and 3D Multi-Die Innovations
Location: West Building, 100 Level, Room 101 C
Speaker (Design): Sutirtha Kabir – Synopsys
Design
Tuesday, Oct 7th
1:30pm - 1:50pm MT
Manufacturing to Development to Manufacturing for Circular Collaboration Leveraging AI and Other EDA Advances
Location: West Building, 100 Level, Room 101 C
Speaker (Design): David Kelf – Breker Verification Systems
Design
Tuesday, Oct 7th
1:50pm - 2:10pm MT
Bridging the Silicon Divide: Converging Chip Design and Manufacturing in the Era of High Integration
Location: West Building, 100 Level, Room 101 C
Speaker (Design): Lu Dai – Qualcomm Technologies
Design
Tuesday, Oct 7th
2:10pm - 2:30pm MT
Chip design & manufacturing convergence: 3D design brings multi-physics requirements while manufacturing yield improvements require digital twin modeling and ingesting design data
Location: West Building, 100 Level, Room 101 C
Speaker (Design): Joe Kwan – Siemens EDA
Design
Tuesday, Oct 7th
2:30pm - 2:50pm MT
Multiphysics & Multiscale Challenges and Solutions for 3D Heterogenous Integration
Location: West Building, 100 Level, Room 101 C
Speaker (Design): Sudarshan Mallu – Ansys, part of Synopsys
Design
Tuesday, Oct 7th
2:50pm - 3:00pm MT
Break
Location: West Building, 100 Level, Room 101 C
Design
Tuesday, Oct 7th
3:00pm - 3:50pm MT
Panel Discussion: The Convergence of Semiconductor Manufacturing and Design
Location: West Building, 100 Level, Room 101 C
Panel Moderator (Design): Ming Zhang – PDF Solutions
Panelist (Design): David Kelf – Breker Verification Systems
Panelist (Design): Lu Dai – Qualcomm Technologies
Panelist (Design): Joe Kwan – Siemens EDA
Panelist (Design): Sutirtha Kabir – Synopsys
Design
Tuesday, Oct 7th
3:50pm - 4:00pm MT
Audience Q & A
Location: West Building, 100 Level, Room 101 C
Panel Moderator: Ming Zhang – PDF Solutions
Design
Tuesday, Oct 7th
4:00pm - 4:05pm MT
Closing Remarks
Location: West Building, 100 Level, Room 101 C
Session Moderator: Bob Smith – SEMI
Design