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  • Tuesday, Oct 7th
    1:00pm - 5:00pm MT
    IEEE - IRDS Packaging Integration – History & Roadmap for AI
    Location: West Building, 100 Level, Room 105 BC
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    1:00pm - 1:05pm MT
    Welcome and Introduction
    Location: West Building, 100 Level, Room 105 BC
    Session Moderator (AP): Mark da Silva, PhD – SEMI
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    1:05pm - 1:20pm MT
    Session Overview
    Location: West Building, 100 Level, Room 105 BC
    Speaker (AP): Dev Gupta – APSTL
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    1:20pm - 2:10pm MT
    History of Advanced Packaging & Applications to AI
    Location: West Building, 100 Level, Room 105 BC
    Speaker (AP): Dev Gupta – APSTL
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    2:10pm - 2:40pm MT
    IEEE-IRDS: The Comprehensive Semiconductor Roadmap That Has Driven the Industry for Three Decades
    Location: West Building, 100 Level, Room 105 BC
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    2:40pm - 3:00pm MT
    Break
    Location: West Building, 100 Level, Room 105 BC
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    3:00pm - 3:25pm MT
    New PI Architectures for AI
    Location: West Building, 100 Level, Room 105 BC
    Speaker (AP): Paul Franzon – North Carolina State University
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    3:25pm - 3:50pm MT
    Advanced Packaging Technology Gaps for Future PI for AI & H
    Location: West Building, 100 Level, Room 105 BC
    Speaker (AP): Dev Gupta – APSTL
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    3:50pm - 4:15pm MT
    New Dense Interconnects for AI
    Location: West Building, 100 Level, Room 105 BC
    Speaker (AP): Laura Mirkarimi – Adeia
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    4:15pm - 4:40pm MT
    Advanced Lithography for Dense Package Interconnects on Large Panels
    Location: West Building, 100 Level, Room 105 BC
    Speaker (AP): Koichiro Saito – Ushio America, Inc.
    Speaker (AP): Yu Takada – Ushio
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    4:40pm - 5:00pm MT
    Q&A and Wrap up
    Location: West Building, 100 Level, Room 105 BC
    Session Moderator (AP): Dev Gupta – APSTL
    Heterogeneous IntegrationAdvanced Packaging
  • Tuesday, Oct 7th
    5:00pm - 6:00pm MT
    IRDS Session Happy Hour
    Location: West Building, 100 Level, Room 105 BC
    Heterogeneous IntegrationNetworkingAdvanced Packaging
  • Wednesday, Oct 8th
    10:00am - 12:30pm MT
    Morning Session: AI for Power Efficient and High Bandwidth Interconnect Systems
    Location: West Building, 100 Level, Room 105 BC
    Heterogeneous Integration
    Sponsor 
  • Wednesday, Oct 8th
    10:00am - 10:10am MT
    Welcome Remarks and Agenda Overview
    Location: West Building, 100 Level, Room 105 BC
    Session Moderator (HI): William Chen – Heterogeneous Integration Roadmap, IEEE EPS
    Session Moderator (HI): Ravi Mahajan, PhD – Intel
    Heterogeneous Integration
  • Wednesday, Oct 8th
    10:10am - 10:35am MT
    Federated Learning Within the SMART USA Initiative
    Location: West Building, 100 Level, Room 105 BC
    Speaker (HI): Ross Kunz – Idaho National Laboratory
    Heterogeneous Integration
  • Wednesday, Oct 8th
    10:35am - 11:00am MT
    SCOPE - A Digital Twin for Co-Packaged Optics
    Location: West Building, 100 Level, Room 105 BC
    Speaker (HI): Madhavan Swaminathan – Pennsylvania State University
    Heterogeneous Integration
  • Wednesday, Oct 8th
    11:00am - 11:25am MT
    Future of AI Hardware Enabled by Advanced Packaging
    Location: West Building, 100 Level, Room 105 BC
    Speaker (HI): Raja Swaminathan – AMD
    Heterogeneous Integration
  • Wednesday, Oct 8th
    11:25am - 12:25pm MT
    Panel Discussion and Audience Q&A
    Location: West Building, 100 Level, Room 105 BC
    Panel Moderator (HI): Melissa Grupen-Shemansky – SEMI
    Panelist (HI): Christopher Bailey – Arizona State University
    Panelist (HI): Ross Kunz – Idaho National Laboratory
    Panelist (HI): Chunqing Peng – Google
    Panelist (HI): Madhavan Swaminathan – Pennsylvania State University
    Panelist (HI): Raja Swaminathan – AMD
    Heterogeneous Integration
  • Wednesday, Oct 8th
    12:25pm - 12:30pm MT
    Morning Session Wrap-up 
    Location: West Building, 100 Level, Room 105 BC
    Session Moderator (HI): William Chen – Heterogeneous Integration Roadmap, IEEE EPS
    Session Moderator (HI): Ravi Mahajan, PhD – Intel
    Heterogeneous Integration
  • Wednesday, Oct 8th
    2:00pm - 5:15pm MT
    Afternoon Session: Building and Scaling AI: From Design to Productization
    Location: West Building, 100 Level, Room 105 BC
    Heterogeneous Integration
    Sponsor 
  • Wednesday, Oct 8th
    2:00pm - 2:05pm MT
    Afternoon Session Overview
    Location: West Building, 100 Level, Room 105 BC
    Session Moderator (HI): Ravi Mahajan, PhD – Intel
    Session Moderator (HI): William Chen – Heterogeneous Integration Roadmap, IEEE EPS
    Heterogeneous Integration
  • Wednesday, Oct 8th
    2:05pm - 2:30pm MT
    Qualcomm - Presentation Title TBD
    Location: West Building, 100 Level, Room 105 BC
    Speaker (HI): PR Chidambaram – Qualcomm
    Heterogeneous Integration
  • Wednesday, Oct 8th
    2:30pm - 2:55pm MT
    Innovative Advanced Packaging Solutions for AI
    Location: West Building, 100 Level, Room 105 BC
    Speaker (HI): C.P. Hung – ASE
    Heterogeneous Integration
  • Wednesday, Oct 8th
    2:55pm - 3:20pm MT
    The Impact of Policy on Advanced Semiconductors Ecosystem for Aerospace & Defense
    Location: West Building, 100 Level, Room 105 BC
    Speaker (HI): Tim Lee – Boeing & IEEE
    Heterogeneous Integration
  • Wednesday, Oct 8th
    3:20pm - 3:45pm MT
    Material Matters: Why Dielectrics are the Pivot Point in Packaging & Lam Deposition Breakthroughs
    Location: West Building, 100 Level, Room 105 BC
    Speaker (HI): Ming Li – Lam Research
    Heterogeneous Integration
  • Wednesday, Oct 8th
    3:45pm - 4:10pm MT
    Reimaging and Transforming Package Assembly and Test Manufacturing in the AI Era
    Location: West Building, 100 Level, Room 105 BC
    Speaker (HI): Jeff Pettinato – Intel Corporation
    Heterogeneous Integration
  • Wednesday, Oct 8th
    4:10pm - 5:10pm MT
    Panel Discussion and Audience Q&A 
    Location: West Building, 100 Level, Room 105 BC
    Panel Moderator (HI): Audrey Charles – Lam Research
    Panelist (HI): C.P. Hung – ASE
    Panelist (HI): Tim Lee – Boeing & IEEE
    Panelist (HI): Jeff Pettinato – Intel Corporation
    Panelist (HI): Ming Li – Lam Research
    Panelist (HI): PR Chidambaram – Qualcomm
    Heterogeneous Integration
  • Wednesday, Oct 8th
    5:10pm - 5:15pm MT
    Closing Remarks
    Location: West Building, 100 Level, Room 105 BC
    Session Moderator (HI): Ravi Mahajan, PhD – Intel
    Session Moderator (HI): William Chen – Heterogeneous Integration Roadmap, IEEE EPS
    Heterogeneous Integration
  • Wednesday, Oct 8th
    5:15pm - 6:30pm MT
    Heterogeneous Integration Reception
    Location: West Building, 100 Level, Room 105 BC
    Heterogeneous IntegrationNetworking
    Sponsors