SEMI U Programs are available for purchase and can be booked through the a la carte section of the registration form. For more details, click here.

SEMI U

SEMI U: Advanced Packaging (Chiplets, WLP, Flip Chip, 3D Stacking)

Monday, October 6, 2025

8:30am - 5:30pm MT

Location: North Building, 200 Level, 222 A

Instructor(s)

Terry Alford, Ph.D.

This 1-day course addresses IC packaging, assembly, and package/substrate interconnections. It stresses the impact of the IC and end product requirements, i.e., “smaller, better, cheaper” their influence on the manufacturing processes. Topics include area packaging- ball grid arrays, flip chip, fanout, stacking die and chip scale packages, and the assembly technologies – chip & wire, tape automated bonding, and flip chip, as is emerging technologies namely, 3-D and stacked die, and packaging reliability issues. This course is suitable for anyone seeking a better understanding of the assembly and packaging of semiconductor devices.

Learning Objectives:

Identify the wide variety of package types and how they align with different application uses.
Understand chip interconnection technologies (such as wirebond, flip chip or thin film) and chip encapsulation.
Identify the materials and processes used in packaging.
Summarize the current state of the art packages.
Gain a foundational understanding of what packaging is and its importance to the microelectronics industry.