Despite ominous predictions of "the end of scaling", or "the end of Moore's law", The innovation space in semiconductor architecture has simultaneously broadened and accelerated in the era of AI. Not only are new transistor architectures and materials innovations finding renewed interest, but new and disruptive innovations in advanced packaging and chiplet technology are being adopted at a cadence not seen before. Across this spectrum, multiple new enabling lithography technologies like High NA EUV, new mask absorber materials, and multiple applications requiring field-stitching are ready to help accelerate technology adoption. However, there are growing challenges related to entry cost, market fragmentation, and proposed new form factors that must all be systematically addressed. In this talk, we will identify the relationship between the technology and cost challenges in the scaling roadmap, especially as they relate to high-performance computing, and the economic challenges of development, deployment and capitalization of advanced technologies to an ever-evolving customer base.
