With the rapid increase in application space for artificial intelligence, AI era is already here and is driving the innovation in semiconductor chip making. To improve the compute power and performance of AI semiconductor chips, innovation in both front-end device manufacturing as well as back-end packaging (& heterogeneous integration) is needed. In this talk, the focus will be on the former, and on the challenges being faced by logic and DRAM device scaling. Both logic and DRAM technologies are racing towards sub-10nm feature sizes and are on track to adopt disruptive integration architectures in future.
With device scaling, each process area/technology is impacted, bringing new challenges to fabricate devices with reduced features sizes and higher aspect ratios. Herein, we will discuss the associated process challenges with miniaturization and how TEL is innovating across process technologies (clean track, directional etch, isotropic vapor etch, cleans, films) to tackle these challenges and drive the industry roadmap forward.
