Recent technological trends have led to increased global demand for semiconductors to power advanced methodologies such as AI. As a result, semiconductor manufacturers across the world have begun to investigate novel options for process improvement. One frequently suggested methodology to achieve this improvement is to implement a high-fidelity simulation model to virtually represent a process. Connecting the virtual model to the physical asset for prediction or control is called a Digital Twin (DT). As these models come under increasing pressure for faster run-times and higher fidelity, methods to improve the construction of the models themselves are also needed. We argue that despite their extensive use in literature, the current tools used to construct semiconductor simulations are underdeveloped and do not meet the computational speed needed for real-time decision making. Without a standardized tool to build these simulations, their modularity and capacity for growth are heavily limited. In collaboration with Intel, we are producing a DT framework to address the key challenges in semiconductor testing equipment using a modular discrete event simulation coupled with graph machine learning (ML). The modular DES enables lower cost of development for different A/T simulations, while graph ML methods allow for real time policy comparisons. In this poster, wediscuss the initial step to producing this DT framework. Specifically, the implementation of a DES created through a novel library of classes in the Python language designed to build on top of the already existing SimPy library. These classes are designed to automatically handle specific common logical features of semiconductor assembly/test (A/T) processes such as part type restrictions, unit batching, and shared queues. Beyond this logic, our classes are designed with a modular policy system. This system enables users to custom code hot swappable dispatching and resource allocation policies of any complexity down to the individual component level. This design allows users to create modular, adaptable, digital twin-ready simulations with a much lower level of knowledge and effort. Preliminary efficacy of our library is demonstrated through the implementation of a simulation of an A/T process currently used at the Intel Corporation’s A/T facility. Using this simulator, a variety of benchmark simulations are performed and results compared against data provided by Intel. While the current implementation of the simulation is comparatively primitive and lacks required features for a full DT, initial results are promising and demonstrate the library’s efficacy in producing efficient simulation models. These results encourage further feature development and experimentation on larger scale models to ensure accurate predictions in more complicated processes.
