There are several key challenges that continue to plague the semiconductor industry when it comes to test. As design complexity and the associated number of test types and fault models continue to grow, the traditional approach of running a serialized test program sequence leads to an excess of test time, which in turn leads to an overall higher cost of test. In addition, if one were to generate all the needed patterns to satisfy the desired list of ‘wants’ it would be 10x greater than the available vector memory and resources available in a traditional manufacturing environment.
By adoption of an ‘Adaptive Test’ approach, we can address these challenges, and these methods have typically shown a significant reduction in the test time through dynamically adjusting the sequence of test execution based upon real-time test result data. This dynamic approach can reduce the overall cost of test by skipping unnecessary tests, as well as increase the overall quality of test due to the dynamic ability to selectively choose tests to provide more accurate results.
In this paper, we will explore adaptive test through discussion of the practical applications and benefits of on-chip comparison for scan testing of large SoCs highlighting the interaction between Design for Test (DFT) hardware and corresponding Automated Test Equipment (ATE) methods for adaptive test.
On-chip compare is a process which enables efficient testing of identical cores by reducing the overall scan data volume. This feature allows pattern data for a single core to be reused across multiple identical cores, contrasting with traditional scan tests that require unique input and output data for each core.
Implementing an adaptive test approach, such as with On-chip compare, illustrates key advantages in test efficiency and failure detection for complex designs. This leads to several key advantages for the end customer: reduced test time and complexity, and an overall increase in test quality.
In addition, we will cover how advancements in DFT architecture deliver a sophisticated solution which adapts to dynamically changing test scenarios without the need for hardware or software modifications. This architecture allows for dynamic core retargeting, no additional test mode multiplexing logic is required. Other key features include flexibility in shift timing, as well as the unique ability to scale bus width from full capacity down to a single bit, which is particularly useful when dealing with broken bits of the bus or different packaging configurations with limited available IO.
As we will demonstrate in this paper, by strategically leveraging the latest advancements in DFT architecture, the adaptive test methodology will enable a more sophisticated and resource-efficient approach in testing and reducing test program complexity. At the conclusion of our paper, we will clearly demonstrate that an adaptive test methodology when combined with advanced DFT hardware features, indicate what is sure to be the future solution to combating the growing challenges in the semiconductor test industry.
