AI is compressing the compute roadmap—more transistors, more heat, more concurrency—while fragmenting designs into chiplet-based systems. Old assumptions break: faults propagate across dies, thermal and power delivery become first-order design variables, and traditional insertions miss workload-emergent failures. Test is no longer an endpoint; it’s the orchestration layer governing yield, reliability, and time-to-market.
This keynote proposes “Test 2.0”: holistic, data-driven, and thermally aware. We’ll explore how to rebalance content across wafer, die-level, and package-level test insertions; when to trade pattern depth for parallelism; and how application-level workloads expose silent data corruption beyond the reach of scan. We’ll address rapidly intensifying challenges—multi-die thermals, power delivery, co-packaged IP, signal integrity, and advanced package handling—and outline emerging ideas to stabilize guard-bands, shorten ramps, and scale capacity.
Destination: collaborative ecosystems that convert constraints into compounding advantages—higher UPH, faster time-to-yield, and resilient quality at scale.
