Data Integrity and Device Handling Challenges For Expanded Wafer and Device Testing

The demand for 5G, IoT, AI, wearables, and self-driving or electric vehicles demands the highest level of semiconductor performance. The costs of developing, designing, and fabricating monolithic semiconductors using advanced processes have risen to over 70-80% of the total device cost. Various IP integration strategies combine multiple processors, sensors, RF, and memory modules to meet consumer demands for improved performance, reduced size, weight, and power consumption at a lower overall cost. To cost-effectively meet performance demand targets, the semiconductor industry uses advanced packaging and assembly solutions like 2.5D, 3D, and heterogeneous integration, for combining top technologies from various sources. However, the overall performance is limited by the lowest performing die as the number of dies increases. A single failure within these systems presents a worst-case cost scenario, necessitating complex testing requirements with high data quality and integrity. Consequently, IDMs and foundries rely heavily on thorough test coverage before integration and advanced packaging to ensure semiconductor IP is sufficiently validated. Electrical testing is conducted at various stages of the device fabrication process. The test process involves physical "touchdowns" on test structures, scribe lines, wafers, or devices under test using various advanced probe card technologies. Each touchdown has a high likelihood of generating particles and adherent materials, leading to contamination buildup over time. In-situ cleaning approaches address CRES instability, remove debris affecting probe-to-pad alignment, and maintain uptime for high throughput. With the introduction of MEMS-based probe technologies, the industry has developed highly engineered cleaning materials. For high-volume production, even a 0.5% improvement in OEE can be significant due to cumulative benefits over time. Advances in test-cell tooling, die handling, probe cards, and materials are essential for wafer-level testing and improved test methodologies to identify device failures efficiently. Singulated die and chiplet testing yields precise results, ensures known-good-die, and aligns test parameters with packaged parts. The test and assembly process for chiplets demands careful handling of components. Adaptable carriers, essential for accommodating various device XYZ dimensions and ensuring compatibility with equipment, are required for nearly every form factor produced by a fab. Historically, bare die are managed using pocketed solutions like waffle packs, JEDEC trays, tape & reel, and sticky-tape methods such as film frames. Singulated bare die are prone to issues like brittleness, contamination, cracking, and breaking. Novel universal pocketless carried have been developed that eliminate the limitations of molded trays and single-use carrier tapes. Various films and surfaces with numerous microscopic textures have been created such that < 2% of the device area contacts the film, and the holding force is independent of the surface properties. The holding force can be adjusted to low tack for in-process handling, medium tack for shipping bare dies, and high tack for packaged devices. Efficient testing necessitates the use of universal tools and standards. Material and method innovations for improved device testing and die handling for high-volume manufacturing contribute to improved operational equipment effectiveness (OEE). Gel-Pak is dedicated to working with end-users for delivering innovative solutions that optimize handling, testing, and transportation of high-value devices.