Sr. Director Amkor Technology Inc. Tempe, AZ, United States
There are ample merits of chiplet based designs. Chiplet based packages are allowing OSATs to pack in multiple reticles worth of die within a single package. High performance compute packages include processor die, I/O die, High Bandwidth Memory (HBM) die or die stacks, accelerator die for Artificial Intelligence (AI), for instance. Each of these die may be sourced from different fabrication technologies. Their fabrication technologies and their function and performance drive distinctly different thermal requirements. The chiplet layout topologies around the substrate within the package impact the thermal performance in numerous ways. Increasing logic content is driving the need for high pin count devices. Higher pin count is driving an increase in the package size.
This poster puts the spot light on Active Thermal Control (ATC) requirements for Advanced Packages briefly defined above. Wafer Level test is being challenged by pad pitches that enable micro-pads and hybrid bonding packaging technologies. Package handlers are in the critical path of the manufacturing test work flow. Thermal management for the duration of Burn In Test insertion, Final Test insertion and System Level Test insertion are vital. This poster will describe the thermal challenges and steps we are taking to prepare the supply chain to deliver capabilities per the product deployment schedules.
