GaN High Electron Mobility Transistors with Novel Dielectrics and Etching for Power Electronics

Wide bandgap (WBG) semiconductor GaN is an emerging technology of choice for the next-generation efficient, lightweight, small-form-factor and robust power electronic devices, integrated circuits (ICs), and systems. AlGaN/GaN high electron mobility transistors (HEMTs) are especially attractive for high-power and high-frequency power conversions due to large bandgap, high critical electric field and the high-mobility two-dimensional electron gas (2DEG) at the AlGaN/GaN heterostructure. Two of the major challenges facing GaN HEMTs include gate leakage and reliability, and robust normally-off operation. In this presentation, we will utilize a material-device co-design approach to advance the performance and robustness of GaN HEMTs using novel dielectrics, interface engineering, and nanofabrication processes.
Compared with traditional Schottky-gate AlGaN/GaN HEMTs, metal-insulator-semiconductor HEMTs (MISHEMTs) can dramatically suppress the gate leakage and improve gate stability. BN can be a potential gate dielectric for GaN HEMTs due to low interface states, high thermal conductivity, and high breakdown strength. In this work [1], we investigated low-temperature (400 °C) chemical vapor deposition-grown boron nitride (BN) as the gate dielectric for AlGaN/GaN MISHEMTs on Si. Comprehensive material characterizations were performed to analyze the deposited BN dielectric. Compared with conventional Schottky-gate HEMTs, the MISHEMTs exhibited significantly enhanced performance with 1000X lower reverse gate leakage current, a lower off-state current, a higher on/off current ratio, and lower on-resistance. The frequency-dependent conductance measurement unveiled a low interface trap state density (Dit) on the order of 1011 eV−1 for the BN/HEMT interface.
Normally-off operation or enhancement-mode (E-mode) GaN HEMTs are highly desired for power electronics due to simple drive circuit and fail-safe operation. Gate recess via dry etching is one of the commonly used methods to achieve E-mode GaN HEMTs. However, traditional dry etching process causes damage in the gate trench, leading to unreliable device performance. In this work [2], we developed a simple gate recess etching technique with low etching damage for E-mode GaN HEMT. The gate recess was formed by two-step high-low-power ICP etching. The reference device only had high-power etching gate recess. It was found that the device with high-low power etching showed increased on-current, reduced gate leakage current and threshold voltage dispersion, and reduced hysteresis with 2X reduced interface states. Device reliability testing, including gate step stress, PBTI, and TDDB, also showed the advantages of the device with high-low-power gate recess. This work showed an easy-to-implement approach for realizing high-performance low interface trap E-mode GaN MISHEMT.

References:
[1] Z. He, H. Fu, et al., “Reduced trap state density in AlGaN/GaN HEMTs with low-temperature CVD-grown BN gate dielectric,” Appl. Phys. Lett. 125, 042106 (2024).
[2] Z. He, H. Fu, et al., “Electrical and Reliability Study of GaN E-mode MISHEMTs with Two-Step Etching Gate Recess,” submitted, under review (2025).