Professor
Arizona State University
Mesa, AZ, United States
Chris Bailey joined Arizona State University in 2022 where is Professor of Advanced Semiconductor Packaging and Director of the Centre for Advanced Semiconductor Packaging. Prior to this he was Professor of Computational Mechanics & Reliability and Associate Dean for Research at the University of Greenwich, UK. At ASU, Chris is leading on advanced semiconductor packaging, he is PI on an SRC funded project on Thermo-Mechanical Modelling and Reliability of Redistribution Layers, and Co-I on several large US-Chips-Act funded projects such as SWAP-Hub, SHIELD, and ITSI.
Chris has published 400+ archival papers in electronics packaging and received $40M+ from Government and Industry to support his research activities. From 2000-2010, he was Co-I on the UK Innovative Electronics Manufacturing Research Centre (IEMRC), and from 2010-2020 he was a Co-I on the UK Centre for Power Electronics. He has served on several UK Government and Research Council bodies including Engineering and Physical Sciences Research Council (EPSRC) Peer Review College (2016-2022), and the UK Research Excellence Framework (2010-2014).
He has been an invited Keynote speaker at numerous conferences internationally and was recently the Program Chair for the IEEE Int Conf. on Physical Assurance and Inspection of Electronics, PAINE, 2024. Chris was the Royal Society/Kao Tong Po Visiting Professor to Hong Kong, and in 2018 and 2022, he was a Visiting Professor to Indian Institute of Technology, Kharagpur. In 2022, he received the IEEE Electronics Packaging Society David Feldman Award and in 2024 he received the Societies Region 8 (Europe) award.
Since 2010, Chris has served on the IEEE Electronics Packaging Society Board of Governors, and from 2020-2021, he was the President of the society. He is an associate editor for the IEEE Transactions of Components, Packaging, and Manufacturing Technology; Chapter Chair for the IEEE-EPS Phoenix Chapter; and co-chair for the Co-Design and Modelling & Simulation chapters for the Heterogeneous Integration Roadmap (HIR).
Panel Discussion and Audience Q&A
Wednesday, October 8, 2025
11:25am - 12:25pm MT