Software Architect
Teradyne
Wake Forest, NC, United States
Paddy Kannampalli
Software Architect, Teradyne | AI Innovator in Semiconductor Test & Manufacturing
Paddy Kannampalli is a Software Architect at Teradyne, where he leads the design and implementation of advanced Automated Test Equipment (ATE) solutions for semiconductor devices. His work spans testing device under test (DUTs) over GPIOs, USB, and PCIe interfaces, enabling robust validation across diverse device architectures. Paddy has also architected scalable workflow solutions that streamline device testing in high-volume manufacturing environments, driving efficiency and precision from lab to fab.
A passionate advocate for data-driven innovation, Paddy actively contributes to SEMI forums focused on integrating artificial intelligence into semiconductor manufacturing. His current efforts center on correlating metrology and electrical test data to accelerate time-to-market while enhancing device quality—an approach that bridges design, test, and analytics in transformative ways.
Paddy is a contributing member of the IEEE Heterogeneous Integration Roadmap (HIR), specifically within the Data Analytics chapter, where he helps shape the future of intelligent test strategies and predictive diagnostics. He holds a Master’s degree in Computer Engineering from the University of California, Riverside, and has a U.S. patent related to semiconductor test automation.
At SEMICON West, Paddy brings a unique blend of architectural rigor, AI foresight, and collaborative spirit—offering insights into how next-generation test platforms and intelligent data fusion are reshaping the semiconductor lifecycle.
Thursday, October 9, 2025
11:15am - 11:30am MT