This work proposes an artificial-intelligence (AI)-based decision tree concept for fabrication-informed optimization of wafer-scale fabric. The optimization process considers high-resolution deep ultraviolet (DUV) EX4 (22mm × 22mm) reticles, large-field (44mm × 44mm) I-line stitched reticles, and waferscale laser direct-write (LDW) lithography. These fabrication techniques are combined to enable a circuit area to include the entire 200mm wafer, enabling a full system-on-wafer (SoW) form factor. To demonstrate the scalability and viability of heterogeneous integration, we fabricated micro-bumps on a 200mm wafer with a bump size down to 1.5µm at a 5µm pitch. We further developed various thermal solutions capable of handling twenty 20mm x 20mm chips uniformly spaced on a 200mm wafer, to address the challenging thermal budget constraints of a SoW approach. Air cooling with heat pipes, traditional liquid cold plates, micro-channel liquid cold plates, and jet impingement on silicon are used to evaluate the thermal performance of SoWs. These thermal analyses indicated that high-power chips can be handled with an appropriate thermal architecture.
