Automatic Fault Isolation Through Smart Layout Tracing and Time Series-based Image Analysis

In modern semiconductor manufacturing, rapid and accurate fault isolation remains critical for successful yield ramp and sustainable production. With increasing device complexity featuring nanometer-scale features and billions of transistors, traditional layout net tracing methodologies face significant throughput challenges, often requiring hours to analyze single cells and identify defective polygons. This bottleneck severely impacts engineering resources and volume production capabilities in competitive semiconductor environments.
This paper presents a highly automated approach that dramatically improves fault isolation turnaround time through intelligent integration of voltage contrast (VC) image analysis with optimized layout tracing techniques. Our methodology enables precise defect location identification by three key technological advances. We first established a sequential trace of connected polygons derived from layout design data. This sophisticated tracing engine enables comprehensive net mapping while handling branching structures and hierarchical designs while foregoing net indexing. To further enhance processing efficiency, our implementation leverages a rapid layout file access system that reduces OAS file loading time from 30 minutes to less than 3 seconds, enabling real-time analysis of complex layout data without lengthy preprocessing delays.
Second, our image registration algorithm precisely aligns these layout traces with voltage contrast (VC) images captured during scanning electron microscope (SEM) inspection. This critical alignment enables automated extraction of polygon intensity values in sequential order along the trace path—a fundamental advancement over manual inspection methods. By processing polygon intensities as an ordered sequence following electrical signal flow, our system transforms visual inspection into quantifiable data analysis.
Finally, we apply advanced time series change point detection algorithms to this sequence of polygon intensities, automatically identifying significant intensity transitions between connected polygons. These transition points precisely pinpoint defect locations where electrical connectivity is compromised. The system specifically targets bright-to-dark transitions that reliably indicate broken connections, while filtering out normal intensity variations.
Implementation in a high-volume production line demonstrated remarkable improvements, reducing average fault isolation time from the previous 1-3 hours to just 30 seconds per site—a 99% reduction. This dramatic efficiency gain has released critical engineering resources while accelerating yield learning cycles. The fully automated workflow eliminates manual tracing and visual inspection steps, enabling 24/7 operation and integration with existing failure analysis pipelines.
The system has been successfully deployed across multiple product platforms and technology nodes, where it has identified hundreds of defect patterns with over 80% accuracy. By dramatically accelerating fault isolation while maintaining high accuracy, our approach delivers significant business impact through faster yield learning cycles and more efficient utilization of failure analysis resources in high-volume semiconductor manufacturing.