Even as device pins for test have become more precious, test bandwidth requirements relentlessly grow. Two technical developments address these problems. Recent technology changes have led to designs requiring dedicated test access ports for scan and other production test data, with very limited physical space for such a port on the chip. Modern SCAN fabrics like Tessent SSN can be combined with high-speed digital I/O cells and mux/demux logic or PCIe to transport test data and results through a limited number of I/Os at multi-gigabit speed. This presentation explains how the combination of high speed digital tester channels, Tessent FastIO SSN and Gigabit GPIO cells will help to maximize scan throughput and minimize the number of physical I/Os connected to the ATE. This method can be utilized on the already installed base of testers and fits seamlessly into the existing infrastructure for pattern translation and diagnosis data collection. This presentation will also explain the rapidly developing technology of using HSIO such as PCIe or USB in combination with Tessent’s In System Test for delivery of test content and how that will not just provide maximal throughput but also open new applications for structural testing.
