Academician and Sr. Director TSMC San Jose, CA, United States
As packaging continues to increase in complexity to meet the growing demands of the compute market, vertically stacked 3D integrated chips (3DICs) rely on advanced interconnect technologies to improve power efficiency, reduce signal latency, and enable higher integration density. However, stacked dies can introduce defects from various sources, such as power leakage, interconnect failures, or structural weaknesses. Detecting these defective dies with traditional testing methods is challenging, often requiring stress tests and detailed analysis. To address these challenges, Teradyne and TSMC have partnered to develop a machine learning–based pattern recognition algorithm to detect defective dies using time-series current profiles. This presentation will cover the design of function-like ATPG patterns, the resulting data, the the developed algorithms to detect these defects, including both feature-based and waveform signature-based approaches, and the results.
