This article provides an in-depth analysis of the current challenges in post-silicon validation and how a standardized software framework can address each of them and create a scalable and adaptable testing environment in the dynamic landscape of semiconductor post-silicon validation engineering.
Semiconductor devices have become increasingly sophisticated to meet the demands of fast-paced industries. This requires more extensive and intricate testing processes. However, the tools used in post-silicon validation are typically fragmented across different teams and locations that develop and maintain software catering to their needs. While some of these software interfaces are built from scratch, others leverage a variety of commercial off-the-shelf (COTS) test sequencers. This disparity and non-uniformity in the software interfaces and toolchain limit data collection and correlation. As a result, engineering teams waste significant effort in developing similar functionality across different groups. With more IP being integrated into a single chip, previously distinct validation teams must now work with each other to get the product out into the market faster.
To address these growing complexities, it is essential to adopt a framework that can: 1. Reuse software assets and code across teams, projects, and programs. 2. Enable an intuitive debug environment for designers and validation engineers with increased automation. 3. Easy onboarding of new engineers into the validation activity. 4. Despite the apparent simplicity of the primary objectives, challenges arise due to factors such as team size, organizational structure, and other aspects, including software practices and hardware platforms.
Architecting such a framework is essential, and we at Soliton have architected enterprise-scale semiconductor validation and multi-site test frameworks over the last two decades. The framework not only allows testing, but with a rightly considered software architecture enables end-to-end connectivity of requirements, tests, their data, and facilitates better traceability and correlation of results and metrics. In this presentation, we will present designs of different components such as abstracted instrument communication layers, device communication layers, debug bring-up and initial debugging, increased end-to-end automation design, and data logging & reporting modules of the framework in detail that helped our key semiconductor customers(over 300+ engineers) address the issues and enhance their semiconductor validation coverage and reduce time to market of the devices.
Having such a framework does not end with these benefits, but also enables semiconductor validation connectivity to both upstream and downstream components of work, and helps connect EDA to ATE. Our work for Analog Devices Inc. has resulted in a 30% efficiency improvement through a first-of-its-kind Lab-to-Fab standardization initiative, achieved by partnering with Soliton. More details about this are covered in this link - https://www.solitontech.com/partnering-with-analog-devices/
We look forward to presenting our work and learnings to accelerate the time-to-market of the semiconductor devices by achieving standardization and end-to-end connectivity of the semiconductor lifecycle.
