This work presents a machine learning (ML) based approach to optimize resource allocation in Device Interface Board (DIB) design for both analog and digital chip testing using Teradyne ETS-800 and UltraFLEX/UltraFLEXPlus platforms. DIB design is a complex and manual process that involves mapping hundreds of pins to test instruments across numerous test items, often requiring iterative decisions to satisfy electrical, timing, and routing constraints. This complexity makes the process time-consuming and error-prone, often stretching over several weeks. We developed a two-stage Python framework featuring automated instrument recommendation followed by channel assignment with simplified routing validation. The system is trained on data extracted from hundreds of historical Teradyne DIB designs, enabling it to learn patterns for efficient resource allocation. By integrating ML into the design flow, the solution can significantly reduce manual effort from weeks to days and improves design accuracy, minimizing board revisions and accelerating test time.
