Senior Director ASE Group / CRD / Corporate Test R&D Kaohsiung, Kaohsiung, Taiwan (Republic of China)
In-process testing in hybrid packaging assembly is becoming challenging due to its impact on assembly quality, die loss, and testing costs. Identifying appropriate in-process test solutions to improve assembly yield will be a key topic in the discussion.
Regarding in-process testing, there are in-process open-short test and in-process function test being discussed normally. In preparing in-process test, ATE/Instrument, Loadboard, Socket, and Handler are the major items to be evaluated first.
Taking the in-process open-short test as an example, three types of connection methods are used between the ATE/instrument and the test loadboard/tooling in the market. Each method has a maximum pin count limitation for testing, which poses challenges when dealing with hybrid packages, especially as pin counts continue to increase.
As for test socket, larger device (DUT) will have warpage issue. Test socket also will have warpage when pin counts > 12K pins. Making good contact between DUT and test socket will be another challenge.
Regarding the test handler, hybrid devices with higher pin counts and larger dimensions will require big changes in the handler design. Thermal control of the DUT (such as Network and HPC devices) will be another key factor in designing the handler to test the DUT at the expected temperature.
As for the in-process functional test, it is the right tool to identify assembly defects. DFT (such as BIST, IEEE 1838, UCIE ...) within the die is required to design by chip designers. There are a few more aspects to consider: how to minimize tester configuration for assembly defect monitoring on the assembly line, power and signal integrity to the DUT, thermal control during testing, and so on. DFT design in the die and overall test cost will be key factors to evaluate.
To summarize: Due to higher and higher BOM and assembly complexity of hybrid package, how to alert assembly defect to save die and material are to be considered from NPI stage. Chip designer, assembly process, test team have to collaborate closely for in-process test at early stage. How to balance test fault coverage vs. test cost for in-process test will be the major challenging.
