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    Jun He

    Vice President, Operations, Advanced Packaging Technology & Service
    Taiwan Semiconductor Manufacturing Corporation (TSMC)

    Dr. He is Vice President of Advanced Packaging Technology and Service at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). As industry veteran with over 30 years of semiconductor development experience, his current responsibility spans across company's 3DIC packaging manufacturing and testing technology development/operation. His organization spearheaded the fast expansion of CoWoS capacity supporting AI eco-system. In additional to relentless push for better 3DIC yield and cycle time, his organization’s track record on annual cadence of steep ramping new backend technologies provides critical building blocks for HPC/mobile markets. His another focus is expanding TSMC 3DIC manufacturing network by collaborating closely with OSAT partners to further accelerate capacity expansion. By collaborating with substrate, memory, and backend tool/material suppliers, his organization delivers customers an integrated one-stop 3DIC service, significantly shortening time-to-market of customer products with accelerated HVM ramp.

    Dr. He joined TSMC in 2017 as Senior Director of Advanced Technology Quality and Reliability. In this role, he was leading the development of analytical and test methodology to effectively detect reliability defects as well as screen risky Si wafers and packaging units. Such innovations accelerated launch and steep production ramp for 7nm and 5nm technologies. Dr. He also revamped TSMC’s quality management system for incoming materials in 2019 and strengthened collaborative relationship with key suppliers. In 2020, Dr. He was promoted to Vice President of the Quality and Reliability Organization at TSMC. During this period, he further established a foundry eco-system, such as incoming materials qualification, reliability and certification of new process technology & design IP, manufacturing quality as well as enabling customers for their product qualification and ramp. His contributions supported the development and production ramp for 3nm technology.

    Prior to joining TSMC, Dr. He was a senior director at Intel Corporation, with excellent technical track record and extensive leadership experience in Si and packaging process technology development and global manufacturing. Up to now, Dr. He holds 141 patents globally, including 60 U.S. patents and published over 50 papers in international conferences and peer-reviewed technical journals. He received his B.S. degree in Physics and Ph.D. in Materials Science from University of CA, Santa Barbara.

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